Micro Electronics Research Lab - UITU

Verification in hardware design is a time-consuming and complex task as well as requires manual effort to update UVM testbench components...

This project focuses on integrating a Ternary Content Addressable Memory (TCAM) module into the Chipyard SoC framework to enable high-speed parallel...

AEGIS automates hardware verification by using AI to generate optimized test cases. Parses Specifications: Extracts key features (interfaces,...

This project aims to develop and benchmark high-performance applications that leverage the modular SoC-Now platform, which integrates RISC-V cores, a...

With the increasing adoption of RISC-V as an open-source Instruction Set Architecture (ISA), there is a growing need for effective and reusable...

Summary The project aims to enhance Nucleus RV Core by adding the RISC-V Vector Extension (RVV v1.0) as a co-processor. Key objectives include...

The "Baby Kyber Accelerator" project aims to address the increasing demand for secure communication by developing a specialized hardware accelerator...

This project involves generating layouts and GDSII files for IPs produced with OpenTCAM, utilising diverse memory structure configurations. TCAM IPs...