CHIPS Alliance
Open source IP, tools & standards for ASIC/FPGA
- 12
- Projects
- 3
- Years accepted
- 4
- In 2024
Projects by year
122024
4 acceptedShow
Our "Support Zvk in T1" project aims to upgrade the T1 processor by adding Zvk, a cryptographic feature from the RISC-V architecture, enhancing its...
I, Muddassir Ali, a final-year Computer Systems Engineering undergraduate student from Pakistan, aim to contribute to the OpenROAD project by...
Relational Framework for Prompt-based Automatic Layout Generation with Glayout
Accepted project · by Chetanya Goyal
The proposal seeks to build upon an existing relational framework that facilitates the generation of DRC-compliant analog layouts through...
This Project adds GDS input and output features to OpenRoad. It would replace the current GDS manipulation scheme, which is through Klayout, and...
2023
5 acceptedShow
Implement Zc RISC-V ISA Extension in Rocket Chip
Accepted project · by Abdul Wadood
This project aims to add support for the RISC-V Code size reduction extension (Zcb, Zcmp, Zcmt) to Rocket Core and perform the architectural testing...
F4PGA is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. Currently,...
1st CLasS (Custom Logic as a Service) for Local FPGA Deployment using F4PGA
Accepted project · by Ali Sajjad
1st CLasS framework is an open-source project that deals with the deployment of a custom kernel on AWS EC2 instance cloud FPGAs with fully automated...
Implementation of a Common Python Framework for OpenFASoC Generators
Accepted project · by Harsh Khandeparkar
OpenFASoC is a project focused on creating fully automated user specifications to GDS generation flow using open-source tools. OpenFASoC uses tools...
Makerchip Flows: A Suite of EDA Flow integrations for TL-Verilog ecosystem
Accepted project · by Shrihari
Makerchip Flows aims at developing EDA flows for TL-Verilog leveraging Edalize backend, for open source tools/flows like yosys, Openlane, F4PGA,...
